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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. tps50602-sp slvsdj9 ? october 2018 tps50602-sp radiation hardened 3-v to 7-v input, 12-a single, 6-a dual output synchronous buck converter 1 1 features 1 ? 5962r18207: ? radiation hardened up to tid 100 krad(si) ? single event latchup (sel), single event burnout (seb), and single event gate rupture (segr) immune to let = 75 mev-cm 2 /mg ? set/sefi cross-section plot available ? peak efficiency: 95% (v o = 3.3 v) ? integrated 48-m /37-m mosfets (pvin = 5 v) ? power rail: 3 to 7 v on vin ? 12-a maximum output current in single output configuration and 6-a maximum output current in dual output configuration ? fixed 500-khz switching frequency using internal oscillator or external clock between 100 khz to 1 mhz at 180 out of phase ? 0.804-v 1.5% voltage reference over temperature, radiation tolerance and line and load regulation ? monotonic start-up into pre-biased outputs ? adjustable soft start through external capacitor ? input enable and power-good output for power sequencing ? power good output monitor for undervoltage and overvoltage ? adjustable input undervoltage lockout (uvlo) ? 64-pin thermally-enhanced ceramic quad flatpack package (hfg) ? engineering evaluation (/em) samples are available (1) 2 applications ? space satellite point of load supply for fpgas, microcontrollers, data converters and asics ? space satellite payloads ? radiation hardened and tolerant point of load applications ? available in military ( ? 55 c to 125 c) temperature range 3 description the tps50602-sp is a dual tps50601a-sp die, tid and see radiation hardened, 7-v, 12-a single output or 6-a dual output synchronous step-down converter, which is optimized for ultra small form factor designs. this is achieved integrating highly efficiency high-side and low-side mosfets and excellent thermal performance. further space savings are achieved through the dual output configuration, which reduces the overall solution size if multiple 6-a rails are needed. the output voltage startup ramp is controlled by the ss/tr pin which allows operation as either a stand alone power supply or in tracking applications. power sequencing is also possible by correctly configuring the enable and the open drain power good pins. thermal shutdown disables the part when die temperature exceeds thermal shutdown temperature. device information (2) part number grade package 5962r1820701vxc rha ? 100 krad(si) hfg (64) tps50602hfg/em engineering evaluation (1) (1) these units are intended for engineering evaluation only. they are processed to a noncompliant flow. these units are not suitable for qualification, production, radiation testing or flight use. parts are not warranted for performance over the full mil specified temperature range of ? 55 c to 125 c or operating life. (2) for all available packages, see the orderable addendum at the end of the data sheet. dual output configuration efficiency at vin = pvin = 3.3 v tps50602-sp phase1 vsense1 phase2 vsense2 pgnd2 thermal pad pgnd1 vout1 vout2 pvin1 vin1 vin2 sstr1 rt1 comp1 sstr2 rt2 comp2 sync1 sync2 refcap1 refcap2 pvin2 advance information load per die (a) e?ciency (%) 0 1 2 3 4 5 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -55c 25c 125c vin = 3.3 v f = 500 khz sw includes 2 outputs technical documents support &community ordernow productfolder tools & software
2 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 6 6.6 typical characteristics .............................................. 8 7 detailed description .............................................. 9 7.1 overview ................................................................... 9 7.2 one of two dice of tps50602-sp functional block diagram .................................................................... 10 7.3 feature description ................................................. 10 7.4 device functional modes ........................................ 18 8 application and implementation ........................ 19 8.1 application information ............................................ 19 8.2 typical application ................................................. 19 9 power supply recommendations ...................... 26 10 layout ................................................................... 26 10.1 layout guidelines ................................................. 26 10.2 layout example .................................................... 27 11 device and documentation support ................. 28 11.1 documentation support ........................................ 28 11.2 community resources .......................................... 28 11.3 trademarks ........................................................... 28 11.4 electrostatic discharge caution ............................ 28 11.5 glossary ................................................................ 28 12 mechanical, packaging, and orderable information ........................................................... 28 12.1 device nomenclature ............................................ 28 4 revision history date revision notes october 2018 * initial release. advance information
3 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated (1) thermal pad and package lid are internally connected to gnd. 5 pin configuration and functions 64-pin cqfp top view pin functions pin i/o description no. name 1, 33 gnd ? return for control circuitry/thermal pad (1) . 2 en2 i enable pin for die 2. this pin has an internal pullup so if left floating, the device is still enabled. adjust the input undervoltage lockout (uvlo) with two resistors. 3 rt2 i/o in internal oscillation mode, a resistor is connected between the rt pin and gnd to set the switching frequency for die 2. a resistor corresponding to 500 khz must be connected to this pin. 4 sync2 i/o external system clock input for die 2. the clock from sync1 is connected to this pin to run at 500 khz. 5 vin1 i supplies the power to the controller for die 1. 6, 7, 8, 9, 10, 11, 12, 13 pvin1 i power input for die 1. 14, 15, 16, 17, 18, 19, 20 pgnd1 ? return for low-side power mosfet for die 1. advance information gnd en2 rt2 sync2 vin1 pvin1 pvin1 pvin1 pvin1 pvin1 pvin1 pvin1 phase1 phase1 phase1 phase1 phase1 pvin2 pgnd2 pgnd2 pgnd2 pgnd2 phase1 phase1 refcap1 vsense1 comp1 sstr1 pwrgd1 phase2 phase2 phase2 phase2 phase2 phase2 phase2 refcap2 vsense2 comp2 sstr2 pwrgd2 pgnd2 pvin2 pvin1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 en1 sync1 vin2 pvin2 rt1 gnd pvin2 pvin2 pvin2 pvin2 pvin2 pgnd2 pgnd2 1 64 63 62 61 60 59 58 57 56 55 54 53 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 thermal pad (14 x 12 mm)
4 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin i/o description no. name 21, 22, 23, 24, 25, 26, 27 phase1 o switch node for die 1. 28 refcap1 o capacitor for internal reference. a 470 nf is recommended to be connected between refcap1 pin and gnd. 29 vsense1 i inverting input of the gm error amplifier for die 1. 30 comp1 i/o error amplifier output and input to the output switch current comparator. connect frequency compensation to this pin. 31 sstr1 i/o slow-start and tracking. an external capacitor connected to this pin sets the internal voltage reference rise time. the voltage on this pin overrides the internal reference. it can be used for tracking and sequencing. 32 pwrgd1 o power good fault pin is an open-drain connection. power good fault pin. asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or en shutdown, or during slow start. 34 en1 i enable pin for die 1. this pin has an internal pullup so if left floating, the device is still enabled. adjust the input undervoltage lockout (uvlo) with two resistors. 35 rt1 i/o resistor to set switching frequency. rt1 should be left floating to generate an output clock at the sync1 pin. 36 sync1 i/o external system clock input for die 1. this pin outputs a 500 khz clock signal at 180 out of phase from the internal clock from die 1. this clock is used to drive sync2. 37 vin2 i supplies the power to the controller for die 2. 38, 39, 40, 41, 42, 43, 44, 45 pvin2 i power input for die 2. 46, 47, 48, 49, 50, 51, 52 pgnd2 ? return for low-side power mosfet for die 2. 53, 54, 55, 56, 57, 58, 59 phase2 o switch node for die 2. 60 refcap2 o capacitor for internal reference. a 470 nf is recommended to be connected between refcap2 pin and gnd. 61 vsense2 i inverting input of the gm error amplifier for die 2. 62 comp2 i/o error amplifier output and input to the output switch current comparator. connect frequency compensation to this pin. 63 sstr2 i/o slow-start and tracking. an external capacitor connected to this pin sets the internal voltage reference rise time. the voltage on this pin overrides the internal reference. it can be used for tracking and sequencing. 64 pwrgd2 o power good fault pin is an open-drain connection. power good fault pin. asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or en shutdown, or during slow start. advance information
5 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) see derating curve. 6 specifications 6.1 absolute maximum ratings over operating temperature (unless otherwise noted) (1) min max unit input voltage vin (2) ? 0.3 7.5 v pvin (2) ? 0.3 7.5 en ? 0.3 5.5 vsense ? 0.3 3.3 comp ? 0.3 3.3 pwrgd ? 0.3 5.5 ss/tr ? 0.3 5.5 rt -0.3 5.5 sync -0.3 7.5 output voltage refcap ? 0.3 3.3 v ph ? 1 7.5 ph 10-ns transient ? 3 7.5 vdiff (gnd to exposed thermal pad) ? 0.2 0.2 v source current ph current limit current limit a rt 100 a sink current ph current limit current limit a pvin current limit current limit a comp 200 a pwrgd ? 0.1 5 ma operating junction temperature ? 55 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001, all pins (1) 750 v v (esd) electrostatic discharge charged-device model (cdm), per jedec specification jesd22-c101, all pins (2) tbd v 6.3 recommended operating conditions min nom max unit t j junction operating temperature ? 55 125 c 6.4 thermal information thermal metric tps50602-sp unit hfg (cqfp) 64 pins r jc(bot) junction-to-case (bottom) thermal resistance 0.56 c/w advance information
6 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated (1) measured at pins. (2) ensured by design only. not tested in production. (3) parameter is not tested in production. 6.5 electrical characteristics t a = ? 55 c to 125 c, v in = p vin = 3.0 v to 7.0 v (unless otherwise noted) parameter test conditions min typ max unit supply voltage (vin and pvin pins) pvin operating input voltage 3.0 7.0 v pvin internal uvlo threshold pv in rising 2.50 v pvin internal uvlo hysteresis 450 mv vin operating input voltage 3.0 7.0 v vin internal uvlo threshold v in rising 2.75 3.0 v vin internal uvlo hysteresis 150 mv vin shutdown supply current v en = 0 v 1.35 2.5 ma vin operating ? non switching supply current v sense = v bg 5 10 ma enable and uvlo (en pin) enable threshold rising 1.14 1.18 v falling 1.05 1.11 input current v en = 1.1 v 6.1 a hysteresis current v en = 1.3 v 3.0 a voltage reference voltage reference 0 a iout 6 a, ? 55 to 125 c 0.792 0.804 0.816 v refcap voltage 470 nf 1.211 v mosfet high-side switch resistance (1) pvin=vin= 3.0 v, lead length = 4 mm 52 m ? high-side switch resistance (1) pvin=vin= 5.0 v, lead length = 4mm 48 m ? high-side switch resistance (1) pvin=vin= 7.0 v, lead length = 4 mm 46 m ? low-side switch resistance (1) pvin=vin= 3.0 v, lead length = 4 mm 38 m ? low-side switch resistance (1) pvin=vin= 5.0 v, lead length = 4 mm 37 m ? low-side switch resistance (1) pvin=vin= 7.0 v, lead length = 4mm 36 m ? error amplifier error amplifier transconductance (g m ) (2) ? 2 a < i comp < 2 a, v (comp) = 1 v 1000 1400 2000 s error amplifier dc gain (2) v sense = 0.804 v 10000 v/v error amplifier source/sink (2) v (comp) = 1 v, 100-mv input overdrive -250 115 250 a error amplifier output resistance 7 m ? start switching threshold (2) 0.25 v comp to iswitch gm (2) 22 s current limit high-side switch current limit threshold (3) v in = 7.0 v 11 a low-side switch sourcing current limit (3) v in = 7.0 v 10 a low-side switch sinking current limit v in = 7.0 v 3 a thermal shutdown thermal shutdown 170 c thermal shutdown hysteresis 30 c internal switching frequency internally set frequency rt = open 395 500 585 khz external synchronization sync out low-to-high rise time (10%/90%) cload = 25 pf 70 111 ns sync out high-to-low fall time (90%/10%) cload = 25 pf 6 15.5 ns advance information
7 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) t a = ? 55 c to 125 c, v in = p vin = 3.0 v to 7.0 v (unless otherwise noted) parameter test conditions min typ max unit (4) bench verified. not tested in production. (5) parameter is production tested at nominal voltage with v in = p vin = 5 v. falling edge delay time (4) 180 sync out high level threshold i oh = 50 a 2 v sync out low level threshold i ol = 50 a 600 mv sync in low level threshold pvin=vin= 3.0 v 900 mv sync in high level threshold pvin=vin= 3.0 v 2.45 v sync in low level threshold pvin=vin= 7.0 v 900 mv sync in high level threshold pvin=vin= 7.0 v 4.25 v sync in frequency range (5) percent of program frequency ? 5% 5% 100 1000 khz ph (ph pin) minimum on time measured at 10% to 90% of vin, 25 c, i ph = 2 a 190 235 ns slow start and tracking (ss/tr pin) ss charge current 1.5 2.5 3 a ss/tr to vsense matching v (ss/tr) = 0.4 v 30 90 mv power good (pwrgd pin) vsense threshold v sense falling (fault) 91 % vref v sense rising (good) 94 % vref v sense rising (fault) 109 % vref v sense falling (good) 106 % vref output high leakage v sense = vref, v(pwrgd) = 5 v 30 181 na output low i (pwrgd) = 2 ma 0.3 v minimum vin for valid output v (pwrgd) < 0.5 v at 100 a 0.6 1 v minimum ss/tr voltage for pwrgd 1.55 v advance information
8 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 typical characteristics system efficiency curves ( figure 4 , figure 5 , and figure 6 ) include 2 outputs. figure 1. current sharing figure 2. high-side r ds(on) figure 3. low-side r ds(on) figure 4. efficiency at vin = pvin = 3.3 v, f sw = 500 khz figure 5. efficiency at vin = pvin = 5 v, f sw = 500 khz figure 6. efficiency at vin = pvin = 5 v, f sw = 100 khz (external clock) load (a) current sharing (%) 0 2 4 6 8 10 12 0 20 40 60 80 100 d001 master n55 (%) slave n55 (%) master 25 (%) slave 25 (%) master 125 (%) slave 125 (%) temperature ( q c) on-state resistance (m : ) -55 -35 -15 5 25 45 65 85 105 125 20 25 30 35 40 45 50 55 60 65 70 d002 vin = 3 v (phase #1) vin = 3 v (phase #2) vin = 5 v (phase #1) vin = 5 v (phase #2) vin = 7 v (phase #1) vin = 7 v (phase #2) temperature ( q c) on-state resistance (m : ) -55 -35 -15 5 25 45 65 85 105 125 0 5 10 15 20 25 30 35 40 45 50 d003 vin = 3 v (phase #1) vin = 3 v (phase #2) vin = 5 v (phase #1) vin = 5 v (phase #2) vin = 7 v (phase #1) vin = 7 v (phase #2) load per die (a) efficiency (%) 0 1 2 3 4 5 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 d004 -55 q c 25 q c 125 q c load per die (a) efficiency (%) 0 1 2 3 4 5 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 d005 -55 q c 25 q c 125 q c load per die (a) efficiency (%) 0 1 2 3 4 5 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 d006 -55 q c 25 q c 125 q c advance information
9 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the tps050602-sp is a dual tps50601a-sp die device that can be configured in dual output or single output configuration. each die is a 7-v, 6-a synchronous step-down (buck) converter with two integrated mosfets, a pmos for the high side and a nmos for the low side. to improve performance during line and load transients, the device implements a constant frequency, peak current mode control, which also simplifies external frequency compensation. the 500-khz switching frequency allows for efficiency and size optimization when selecting the output filter components. the device is designed for safe monotonic startup into prebiased loads. the default start up is when vin is typically 3 v. the en pin has an internal pullup current source that can be used to adjust the input voltage uvlo with two external resistors. in addition, the en pin can be floating for the device to operate with the internal pullup current. the total operating current for the device is approximately 5 ma when not switching and under no load. when the device is disabled, the supply current is typically less than 2.5 ma. the integrated mosfets allow for high-efficiency power supply designs with continuous output currents up to 6 a. the mosfets have been sized to optimize efficiency for lower duty cycle applications. the device has a power good comparator (pwrgd) with hysteresis which monitors the output voltage through the vsense pin. the pwrgd pin is an open-drain mosfet which is pulled low when the vsense pin voltage is less than 91% or greater than 109% of the reference voltage vref and asserts high when the vsense pin voltage is 94% to 106% of the vref. the ss/tr (slow start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing during power-up. a small-value capacitor or resistor divider should be coupled to the pin for slow start or critical power-supply sequencing requirements. the device is protected from output overvoltage, overload, and thermal fault conditions. the device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. when the overvoltage comparator is activated, the high-side mosfet is turned off and prevented from turning on until the vsense pin voltage is lower than 106% of the vref. the device implements both high-side mosfet overload protection and bidirectional low-side mosfet overload protections, which help control the inductor current and avoid current runaway. the device also shuts down if the junction temperature is higher than thermal shutdown trip point. the device is restarted under control of the slow-start circuit automatically when the junction temperature drops 10 c (typical) below the thermal shutdown trip point. advance information
10 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 7.2 one of two dice of tps50602-sp functional block diagram 7.3 feature description 7.3.1 vin and power vin pins (vin and pvin) the device allows for a variety of applications by using the vin and pvin pins together or separately. the vin pin voltage supplies the internal control circuits of the device. the pvin pin voltage provides the input voltage to the power converter system. both pins have an input voltage range from 3 to 7 v. a voltage divider connected to the en pin can adjust the input voltage uvlo appropriately. adjusting the input voltage uvlo on the pvin pin helps to provide consistent power-up behavior. 7.3.2 voltage reference the voltage reference system produces a precise voltage reference as indicated in electrical characteristics . 7.3.3 adjusting the output voltage the output voltage is set with a resistor divider from the output (vout) to the vsense pin. ti recommends to use 1% tolerance or better resistors. start with a 10 k for r top and use equation 1 to calculate r bottom . to improve efficiency at light loads, consider using larger-value resistors. if the values are too high, the regulator is more susceptible to noise and voltage errors from the vsense input current are noticeable. advance information error amplifier uvlo current sense oscillator slope compensation and clamp voltage reference vsense_x ss/tr_x comp_x ph_x refcap_x vin_x pgnd_x thermal shutdown en_x enable comparator shutdown 1.14 v logic shutdown pwrgd_x thermal pad/gnd_x power stage & deadtime control logic ls mosfet current limit ov minimum clamp pulse skip i p i h pvin_x uv hs mosfet current comparator current sense overload recovery sync detect sync_x rt_x rt bias v/i pvin 2.75 v uvlo 2.49 v one of two dice
11 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) where ? v ref = 0.804 v (1) 7.3.4 safe start-up into prebiased outputs the device is designed to prevent the low-side mosfet from discharging a prebiased output. during monotonic prebiased start-up, the low-side mosfet is not allowed to sink current until the ss/tr pin voltage is higher than 1.55 v. 7.3.5 error amplifier the device uses a transconductance error amplifier. the error amplifier compares the vsense pin voltage to the lower of the ss/tr pin voltage or the internal 0.804-v voltage reference. the transconductance of the error amplifier is 1400 a/v during normal operation. the frequency compensation network is connected between the comp pin and ground. the error amplifier dc gain is typically 10,000 v/v. 7.3.6 slope compensation the device adds a compensating ramp to the switch current signal. this slope compensation prevents subharmonic oscillations. the available peak inductor current remains constant over the full duty cycle range. 7.3.7 enable and adjust uvlo the en pin provides electrical on and off control of the device. when the en pin voltage exceeds the threshold voltage, the device starts operation. if the en pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low i q state. the en pin has an internal pullup current source, allowing the user to float the en pin for enabling the device. if an application requires controlling the en pin, use open-drain or open- collector output logic to interface with the pin. the device implements internal uvlo circuitry on the vin pin. the device is disabled when the vin pin voltage falls below the internal vin uvlo threshold. the internal vin uvlo threshold has a hysteresis of 150-mv typical. if an application requires either a higher uvlo threshold on the vin pin or a secondary uvlo on the pvin in split-rail applications, then the en pin can be configured as shown in figure 7 , figure 8 , and figure 9 . a ceramic capacitor in parallel with the bottom resistor r 2 is recommended to reduce noise on the en pin as used in the tps50602-sp evaluation module, (see the tps50602-sp evm user's guide, slvub65 ). the en pin has a small pullup current, i p , which sets the default state of the pin to enable when no external components are connected. the pullup current is also used to control the voltage hysteresis for the uvlo function because it increases by i h after the en pin crosses the enable threshold. calculate the uvlo thresholds with equation 2 and equation 3 . figure 7. adjustable vin uvlo advance information r bottom = v ref vout f v ref r top en ip i h vin per die r1 r2 copyright ? 2017, texas instruments incorporated
12 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 8. adjustable pvin uvlo figure 9. adjustable vin and pvin uvlo (2) en ip i h vin per die r1 r2 pvin copyright ? 2017, texas instruments incorporated advance information en ip i h pvin per die r1 r2 copyright ? 2017, texas instruments incorporated r 1 = v start v enfalling v enrising f v st op i p @ 1 f v enfalling v enrising a + i h
13 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) where ? i h = 3 a ? i p = 6.1 a ? v enrising = 1.14 v ? v enfalling = 1.11 v (3) 7.3.8 fixed switching frequency and synchronization (sync) the two dice in the tps50602-sp must be operated at the same switching frequency and at 180 out of phase. there are then 2 main modes of operation: using the internal oscillator mode or using an external clock driving the sync pin. in internal oscillator mode, (500-khz fixed switching frequency), one die must have its rt pin floating so that the synchronous pin becomes the output and there is a phase inversion. this output signal is used to drive the second die. the rt pin of the second die must have its rt pin populated such that the converter frequency of the slave converter must be within 5% of the master converter. this is required because the rt pin also sets the proper operation of slope compensation. in external synchronization mode, the switching frequency could be anywhere between 100 khz and 1 mhz as long as the clocks feeding the 2 dice are 180 out of phase. in this mode of operation, a resistor is connected between the rt pin and gnd. the sync pin requires a toggling signal for this mode to be effective. the switching frequency of the device goes 1:1 with that of sync pin. external system clock-user supplied sync clock signal determines the switching frequency. if no external clock signal is detected for 20 s, then tps50601a-sp transitions to its internal clock, which is typically 500 khz. rt values of the master and slave converter must be within 5% of the external synchronization frequency. this is necessary for proper slope compensation. a resistance in the rt pin is required for proper operation of the slope compensation circuit. to determine the rt resistance for a given switching frequency, use equation 4 or the curve in figure 10 . where ? rt in k ? f sw in khz (4) figure 10. rt vs switching frequency 7.3.9 slow start (ss/tr) the device uses the lower voltage of the internal voltage reference or the ss/tr pin voltage as the reference voltage and regulates the output accordingly. a capacitor on the ss/tr pin to ground implements a slow-start time. equation 5 shows the calculations for the slow-start time (t ss , 10% to 90%) and slow-start capacitor (c ss ). the voltage reference (vref) is 0.804 v and the slow-start charge current (i ss ) is 2 a. advance information f sw - switching frequency (khz) rt (k : ) 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 d001 r 2 = r 1 v enfalling v stop f v enfalling + r 1 k i p + i h o rt(f ) = 67009 x f sw sw -1.0549
14 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) (5) when any of the following 3 scenarios occur; the input uvlo is triggered, the en pin is pulled below 1.05 v, or a thermal shutdown event occurs; the device stops switching and enters low current operation. at the subsequent power-up, when the shutdown condition is removed, the device does not start switching until it has discharged its ss/tr pin to ground ensuring proper soft-start behavior. 7.3.10 power good (pwrgd) the pwrgd pin is an open-drain output. when the vsense pin is between 94% and 106% of the internal voltage reference, the pwrgd pin pulldown is deasserted and the pin floats. ti recommends to use a pullup resistor between 10 k to 100 k to a voltage source that is 5.5 v or less. the pwrgd is in a defined state when the vin input voltage is greater than 1 v but has reduced current sinking capability. the pwrgd achieves full current sinking capability when the vin input voltage is above 3 v. the pwrgd pin is pulled low when vsense is lower than 91% or greater than 109% of the nominal internal reference voltage. also, the pwrgd is pulled low, if the input uvlo or thermal shutdown are asserted, the en pin is pulled low or the ss/tr pin is below 1.55 v. 7.3.11 sequencing (ss/tr) many of the common power-supply sequencing methods can be implemented using the ss/tr, en, and pwrgd pins. the sequential method is shown in figure 11 using two tps50601a-sp devices. the power good of the first device is coupled to the en pin of the second device, which enables the second power supply after the primary supply reaches regulation. figure 11. sequential start-up sequence figure 12 shows the method implementing ratiometric sequencing by connecting the ss/tr pins of two devices together. the regulator outputs ramp up and reach regulation at the same time. when calculating the slow-start time, the pullup current source must be doubled in equation 5 . t ss : ms ; = c ss (nf) v ref (v) i ss ( j a) advance information ss/tr en pwrgd ss/tr en pwrgd per die per die
15 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 12. ratiometric start-up sequence ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network of r 1 and r 2 (shown in figure 13 ) to the output of the power supply that needs to be tracked or another voltage reference source. using equation 6 and equation 7 , the tracking resistors can be calculated to initiate the vout 2 slightly before, after, or at the same time as vout 1 . equation 8 is the voltage difference between vout 1 and vout 2 . to design a ratiometric start-up in which the vout 2 voltage is slightly greater than the vout 1 voltage when vout 2 reaches regulation, use a negative number in equation 6 and equation 7 for v. equation 8 results in a positive number for applications where the vout 2 is slightly lower than vout 1 when vout 2 regulation is achieved. the v variable is 0 v for simultaneous sequencing. to minimize the effect of the inherent ss/tr to vsense offset ( v ss-offset , 30 mv) in the slow-start circuit and the offset created by the pullup current source (i ss = 2 a) and tracking resistors, the v ss-offset and i ss are included as variables in the equations. to ensure proper operation of the device, the calculated r 1 value from equation 6 must be greater than the value calculated in equation 9 . (6) (7) (8) (9) r 1 > 2800 vout 1 f 180 ? v ? v = vout 1 f vout 2 r 2 = v ref r 1 vout 2 + ? v f v ref advance information r 1 = vout 2 + ? v v ref v ss f offset i ss ss/tr per die en pwrgd ss/tr en pwrgd per die
16 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) figure 13. ratiometric and simultaneous start-up sequence 7.3.12 output overvoltage protection (ovp) the device incorporates an output ovp circuit to minimize output voltage overshoot. for example, when the power supply output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. if the vsense pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. after the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state voltage. in some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. this leads to the possibility of an output overshoot. the ovp feature minimizes the overshoot by comparing the vsense pin voltage to the ovp threshold. if the vsense pin voltage is greater than the ovp threshold, the high-side mosfet is turned off, preventing current from flowing to the output and minimizing output overshoot. when the vsense voltage drops lower than the ovp threshold, the high-side mosfet is allowed to turn on at the next clock cycle. 7.3.13 overcurrent protection the device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side and low-side mosfet. 7.3.13.1 high-side mosfet overcurrent protection the device implements current mode control which uses the comp pin voltage to control the turn off of the high- side mosfet and the turn on of the low-side mosfet on a cycle-by-cycle basis. each cycle the switch current and the current reference generated by the comp pin voltage are compared, when the peak switch current intersects the current reference, the high-side switch is turned off. advance information ss/tr per die en pwrgd ss/tr per die en pwrgd vout1 vout 2 r1 r2 r3 r4
17 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.13.2 low-side mosfet overcurrent protection while the low-side mosfet is turned on its conduction current is monitored by the internal circuitry. during normal operation the low-side mosfet sources current to the load. at the end of every clock cycle, the low-side mosfet sourcing current is compared to the internally set low-side sourcing current limit. if the low-side sourcing current is exceeded, the high-side mosfet is not turned on and the low-side mosfet stays on for the next cycle. the high-side mosfet is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. the low-side mosfet may also sink current from the load. if the low-side sinking current limit is exceeded, the low-side mosfet is turned off immediately for the rest of that clock cycle. in this scenario, both mosfets are off until the start of the next cycle. when the low-side mosfet turns off, the switch node increases and forward biases the high-side mosfet parallel diode (the high-side mosfet is still off at this stage). 7.3.14 thermal shutdown the internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175 c (typical). the device reinitiates the power-up sequence when the junction temperature drops below 165 c (typical). 7.3.15 turn-on behavior minimum on-time specification determines the maximum operating frequency of the design. as the unit starts up and goes through its soft-start process, the required duty-cycle is less than the minimum controllable on-time. this can cause the converter to skip pulses. thus, instantaneous output pulses can be higher or lower than the desired voltage. this behavior is only evident when operating at high frequency with high bandwidth. when the minimum on-pulse is greater than the minimum controllable on-time, the turn-on behavior is normal. 7.3.16 small signal model for frequency compensation the device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits shown in figure 14 . in type 2a, one additional high-frequency pole is added to attenuate high-frequency noise. the following design guidelines are provided for advanced users who prefer to compensate using the general method. the step-by-step design procedure described in detailed design procedure may also be used. figure 14. types of frequency compensation the general design guidelines for device loop compensation are as follows: 1. determine the crossover frequency f co . a good starting point is one-tenth of the switching frequency, f sw . 2. r 3 can be determined by: (10) where gm ea is the gm of the error amplifier (1400 s), gm ps is the gm of the power stage (22 s) and vref is the reference voltage (0.804 v). advance information vref vout r1 r3 c1 c2 r2 coea roea gm ea comp vsense type 2a type 2b r3 c1 r 3 = t n f co v out c out gm ea vref gm ps
18 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 3. place a compensation zero at the dominant pole using c 1 and r 3 . c 1 can be determined by (11) 4. c 2 is optional. it can be used to cancel the zero from the equivalent series resistance (esr) of the output capacitor c out . (12) 7.4 device functional modes 7.4.1 fixed-frequency pwm control the device uses fixed frequency, peak current mode control. the output voltage is compared through external resistors on the vsense pin to an internal voltage reference by an error amplifier which drives the comp pin. an internal oscillator initiates the turn on of the high-side power switch. the error amplifier output is converted into a current reference which compares to the high-side power switch current. when the power switch current reaches the current reference generated by the comp voltage level, the high-side power switch is turned off and the low-side power switch is turned on. 7.4.2 continuous current mode (ccm) operation as a synchronous buck converter, the device normally works in ccm under all load conditions. f p = 1 c out r l t n c 1 = c out r l r 3 c 2 = c out r esr r 3 advance information
19 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps50602-sp device is a highly-integrated synchronous step-down dc-dc converter. the device is used to convert a higher dc-dc input voltage to a lower dc output voltage with a maximum output current of 12-a in single output configuration or 6-a in dual output configuration. the tps50602-sp user's guide is available on the ti website (see slvub66 ). the guide highlights standard evm test results, schematic, and bom for reference (basic design equations in following sections are provided for reference only). 8.2 typical application advance information
20 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 8.2.1 12-a single output configuration the tps50602-sp can be configured for a 12-a single output voltage as shown in figure 15 . in this case, the 2 dice in the package run in master-slave configuration at an internal 500-khz switching frequency (internal oscillator) or an external clock but 180 out of phase in both cases. if using internal oscillator, the rt1 pin is left floating since sync1 is used as an output clock signal for sync2. a resistor is then connected to the rt2 pin to set the frequency to 500 khz. please refer to fixed switching frequency and synchronization (sync) section for more details regarding switching frequency configuration. the ss, sstr and vsense pins for each die are connected one to another. figure 15. 12-a single output configuration the design procedure to configure the master-slave operation using the internal oscillator is as follows: gnd en2 tps50602-sp rt2 sync2 vin1 pvin1 pvin1 pvin1 pvin1 pvin1 pvin1 pvin1 phase1 phase1 phase1 phase1 phase1 pvin2 pgnd2 pgnd2 pgnd2 pgnd2 phase1 phase1 refcap1 vsense1 comp1 sstr1 pwrgd1 phase2 phase2 phase2 phase2 phase2 phase2 phase2 refcap2 vsense2 comp2 sstr2 pwrgd2 pgnd2 pvin2 pvin1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 en1 sync1 vin2 pvin2 rt1 gnd pvin2 pvin2 pvin2 pvin2 pvin2 pgnd2 pgnd2 1 64 vout sync vsense vsense sync vsense comp sstr sstr comp advance information
21 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 1. the rt pin of the master device must be left floating. this achieves 2 purposes, to set the frequency to 500 khz (typical) using the internal oscillator and to configure the sync pin of the master device as an output pin with a 500-khz clock, 180 out of phase respect to the internal oscillator of the master device. for more details, see fixed switching frequency and synchronization (sync) section. 2. the rt pin on slave device should be connected to a resistor such that the frequency of the slave device is within 5% of the master's frequency, 500 khz in this case. see figure 10 for reference. 3. sync pin of the master device must be connected to the sync pin of the slave device. 4. only a single feedback network is needed connected to the vsense pin of the master device. therefore, both vsense pins must be connected. 5. only a single compensation network is needed connected to the comp pin of the master device. therefore both comp pins must be connected. 6. only a single soft start capacitor is needed connected to the ss pin of the master device. therefore both ss pins must be connected. 7. only a single enable signal (or resistor divider) is needed connected to the en pin of the master device. therefore both en pins must be connected. 8. since the master device controls the compensation, soft start and enable networks, the factor of 2 must be taken into account when calculating the components associated with these pins. the master-slave mode can also be implemented using an external clock. in such case, a different frequency other than 500 khz can be used. when using an external clock, only the rt and sync pins configuration varies as follows: 1. rt pins of both master and slave device must be connected to a resistor matching the frequency of the external clock being used. see figure 10 for reference. 2. the external clock is connected to the sync pin of the master device. a 10-k resistor to gnd should be connected to the sync pin as well. 3. an inverted clock (180 out of phase respect to the master device) must be connected to the sync pin of the slave device. a 10-k resistor to gnd should be connected to the sync pin as well. 8.2.2 6-a dual output configuration the 6-a dual output configuration of the tps50602-sp allows for great area savings. in this case, the 2 dice in the tps50602-sp can be configured individually as shown in figure 16 but they must run 180 out of phase at an internal 500-khz switching frequency (internal oscillator) or an external clock but. if using internal oscillator, the rt1 pin is left floating since sync1 is used as an output clock signal for sync2. a resistor is then connected to the rt2 pin to set the frequency to 500 khz. please refer to fixed switching frequency and synchronization (sync) section for more details regarding switching frequency configuration. advance information
22 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) figure 16. 6-a dual output configuration gnd en2 tps50602-sp rt2 sync2 vin1 pvin1 pvin1 pvin1 pvin1 pvin1 pvin1 pvin1 phase1 phase1 phase1 phase1 phase1 pvin2 pgnd2 pgnd2 pgnd2 pgnd2 phase1 phase1 refcap1 vsense1 comp1 sstr1 pwrgd1 phase2 phase2 phase2 phase2 phase2 phase2 phase2 refcap2 vsense2 comp2 sstr2 pwrgd2 pgnd2 pvin2 pvin1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 en1 sync1 vin2 pvin2 rt1 gnd pvin2 pvin2 pvin2 pvin2 pvin2 pgnd2 pgnd2 1 64 vout1 vout2 sync1 sync1 advance information
23 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 8.2.3 design requirements this example highlights a design for the tps50601a-sp die (vout1) in the tps50602-sp evaluation module in dual output configuration. for more details, please refer to the evm user's guide (see slvub66 ). a few parameters must be known in order to start the design process. these parameters are typically determined at the system level. for this example, we start with the following known parameters: table 1. design parameters design parameter example value output voltage 2.5 v maximum output current 6 a transient response 1-a load step vout = 5% input voltage 5-v nominal, 4.5 v to 7 v output voltage ripple 20 mvp-p start input voltage (rising v in ) 4.5 v stop input voltage (falling v in ) 4.3 v switching frequency 500 khz (internal oscillator) 8.2.4 detailed design procedure 8.2.4.1 operating frequency in this design, a switching frequency of 500 khz is selected. based on the fixed switching frequency and synchronization (sync) section, the rt1 is left floating and the sync1 pin is used to drive the sync2 pin and the rt2 pin must have a 95.3-k resistor. 8.2.4.2 output inductor selection to calculate the value of the output inductor, use equation 13 . k l is a coefficient that represents the amount of inductor ripple current relative to the maximum output current, i o . the inductor ripple current is filtered by the output capacitor therefore, choosing high-inductor ripple currents impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. in general, the inductor ripple value is at the discretion of the designer depending on specific system needs. typical values for k l range from 0.1 to 0.5. for low output currents, the value of k l could be increased to reduce the value of the output inductor. (13) for this design example, use k l = 0.45 and the inductor value is calculated to be 1.8 h for nominal vin = 5 v. 8.2.4.3 output capacitor selection there are three primary considerations for selecting the value of the output capacitor. the output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. the output capacitance needs to be selected based on the more stringent of these three criteria. the desired response to a large change in the load current is the first criteria. the output capacitor needs to supply the load with current when the regulator can not. this situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. the regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. the output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. equation 14 shows the minimum output capacitance, from the electrical point of view, necessary to accomplish this. (14) l = v inmax f vout i o k l vout v inmax f sw advance information c out > 2 i o f sw ? vout
24 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated where i o is the change in output current, f sw is the regulator switching frequency and vout is the allowable change in the output voltage. for this example, the transient load response is specified as a 5% change in vout for a load step of 1 a. for this example, i o = 1 a and vout = 0.05 2.5 = 0.125 v. using these numbers gives a minimum capacitance of 160 f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the esr is usually small enough to ignore in this calculation. however, for space applications and large capacitance values, tantalum capacitors are typically used which have a certain esr value to take into consideration. equation 15 calculates the minimum output capacitance needed to meet the output voltage ripple specification. where f sw is the switching frequency, vout ripple is the maximum allowable output voltage ripple, and i ripple is the inductor ripple current. in this case, the maximum output voltage ripple is 20 mv. under this requirement, equation 15 yields 168.75 f. (15) equation 16 calculates the maximum esr an output capacitor can have to meet the output voltage ripple specification. equation 16 indicates the esr should be less than 7.41 m . (16) for this specific design, taking into consideration the stringent requirements for space applications, two output capacitors of 330 f (cout = 660 f) with esr = 6 m each have been selected. 8.2.4.4 slow start capacitor selection the slow start capacitor c ss , determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. this is useful if a load requires a controlled voltage slew rate. this is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. the large currents necessary to charge the capacitor may make the tps50601a-sp reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. limiting the output voltage slew rate solves both of these problems. the soft start capacitor value can be calculated using equation 5 . the example circuit has the soft start time set to an arbitrary value of about 4 ms which requires a 10-nf capacitor. in tps50601a-sp, i ss is 2- a typical, and v ref is 0.804 v. 8.2.4.5 undervoltage lockout (uvlo) set point the uvlo can be adjusted using the external voltage divider network formed by r 1 and r 2 . r 1 is connected between vin and the en pin of the tps50601a-sp and r 2 is connected between en and gnd. the uvlo has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. for the example design, the supply should turn on and start switching once the input voltage increases above selected voltage (uvlo start or enable). after the regulator starts switching, it should continue to do so until the input voltage falls below (uvlo stop or disable) voltage. equation 2 and equation 3 can be used to calculate the values for the upper and lower resistor values. for the stop voltages specified in table 1 , the nearest standard resistor value for r 1 is 10 k and for r 2 is 3.4 k . 8.2.4.6 output voltage feedback resistor selection the resistor divider network r top and r bottom is used to set the output voltage. for the example design, 10 k was selected for r top . using equation 1 , r bottom is calculated as 4.77 k . a 4.64-k resistor was used for this design. 8.2.4.7 compensation component selection there are several industry techniques used to compensate dc-dc regulators. for this design, type 2b compensation is used as shown in the small signal model for frequency compensation section. r esr < vout ripple i ripple advance information c out > 1 8 f sw i ripple vout ripple
25 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated first, the modulator pole, f pmod , and the r esr zero, f zmod must be calculated using equation 17 and equation 18 . use equation 19 and equation 20 to estimate a starting point for the closed loop crossover frequency f co , then the required compensation components may be derived. for this design example, f pmod is 0.58 khz and f zmod is 80.36 khz. equation 19 is the geometric mean of the modulator pole and the esr zero and equation 20 is the geometric mean of the modulator pole and one half the switching frequency. use a frequency near the lower of these two values as the intended crossover frequency f co . in this case equation 19 yields 6.82 khz and equation 20 yields 12.03 khz. a frequency of 10 khz is chosen as the intended crossover frequency. (17) (18) (19) (20) now the compensation components can be calculated using equation 10 and equation 11 . the standard values for r 3 and c 1 are 4.02 k and 68 nf, respectively. f zmod = 1 t n r esr c out f pmod = i out t n v out c out advance information f co = f pmod f sw 2 f co = f pmod f zmod
26 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.5 application curve the evaluation module for the tps50602-sp was used to capture a load step response of the device. the testing conditions were: ? vin = pvin = 5 v ? vout = 2.5 v ? load step = 0 a to 5 a ? switching frequency = 500 khz 9 power supply recommendations the tps50602-sp is designed to operate from an input voltage supply range between 3 v and 7 v. this supply voltage must be well regulated and proper local bypass capacitors should be used for proper electrical performance from pvin to gnd and from vin to gnd. due to stringent requirements for space applications, typically additional input bypass capacitors are used. the tps50602-sp evaluation module uses 6, 22- f ceramic capacitors in addition to 3, 150- f tantalum capacitors from pvin to gnd and a 4.7 f and a 0.1 f from vin to gnd. 10 layout 10.1 layout guidelines layout is a critical portion of good power supply design. standard good practices should be applied. some basic guidelines follow: ? the top layer contains the main power traces for pvin, vin, vout, and phase. also on the top layer are connections for the remaining pins of the tps50602-sp and a large top side area filled with ground. ? the top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass capacitor and the output filter capacitor. ? thermal pad can be electrically floating or connected externally. if electrically connected externally then it must be connected to gnd. customer should evaluate their system performance when thermal pad is electrically isolated and thermally conductive. ? preferred approach is that gnd pin should be tied directly to the power pad under the ic and the pgnd. ? the pvin and vin pins should be bypassed to ground with ceramic capacitors placed as close as possible to the pins. ? since the ph connection is the switching node, the output inductor should be located close to the ph pins, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. ? the rt, refcap and comp pins are sensitive to noise so the respective components should be located as close as possible to the ic and routed with minimal lengths of trace. ? the feedback voltage signal vsense should be routed away from the switching node. advance information
27 tps50602-sp www.ti.com slvsdj9 ? october 2018 product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 10.2 layout example figure 17. pcb layout example advance information gnd en2 rt2 sync2 vin1 pvin1 pvin1 pvin1 pvin1 pvin1 pvin1 pvin1 phase1 phase1 phase1 phase1 phase1 pvin2 pgnd2 pgnd2 pgnd2 pgnd2 phase1 phase1 refcap1 vsense1 comp1 sstr1 pwrgd1 phase2 phase2 phase2 phase2 phase2 phase2 phase2 refcap2 vsense2 comp2 sstr2 pwrgd2 pgnd2 pvin2 pvin1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 pgnd1 en1 sync1 vin2 pvin2 rt1 gnd pvin2 pvin2 pvin2 pvin2 pvin2 pgnd2 pgnd2 1 64 63 62 61 60 59 58 57 56 55 54 53 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 thermal pad (14 x 12 mm) as close to the device as possible as close to the device as possible vout2 r top r bottom trace away from switching node c out l close to device and loop as small as possible vout2 r top r bottom trace away from switching node c out l close to device and loop as small as possible
28 tps50602-sp slvsdj9 ? october 2018 www.ti.com product folder links: tps50602-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: tps50602evm-cval evaluation module , slvub66 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 12.1 device nomenclature rha radiation hardness assurance for space systems advance information
package option addendum www.ti.com 27-nov-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ptps50602hfg/em active cfp hfg 64 1 tbd call ti call ti 25 to 25 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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